<1> reset <2> ei ie0 ei iet0 <3> ei <4> di ie0 <5> di ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
208 m pd750108 user's manual (2) example of using intbt, int0 (falling edge active), and intt0 without multiple interrupt processing <1> a reset signal disables all interrupts, setting status 0. <2> int0 is set to be falling edge active. <3> interrupts are enabled by the ei and ei iexxx instructions. <4> on the falling edge of int0, the int0 interrupt service program is started, status is set to 1, and all interrupts are disabled. <5> control is returned from the interrupts by the reti instruction, status 0 is set again, and interrupts are enabled. remark if all the interrupts are used as having the lower priority as shown in this example, saving or restoring the register bank is not necessary if rbe = 1 and rbs = 2 for the main program and register banks 2 and 3 are used, and rbe = 0 for the interrupt service program and register banks 0 and 1 are used. ; rbe = 1, mbe = 0

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reset <2> mov status 0 status 0 status 1 a, #1 mov im0, a clr1 irq0 <3> ei iebt ei ie0 ei iet0 ei <4> int0 <5> reti <1> ; rbe = 0
209 chapter 6 interrupt and test functions (3) nesting of interrupts with higher priority (intbt has higher priority and intt0 and intcsi have lower priority) <1> intbt is specified as having the higher priority by setting of ips, and the interrupt is enabled at the same time. <2> intt0 service program is started when intt0 with the lower priority occurs. status 1 is set and the other interrupts with the lower priority are disabled. rbe = 0 to select register bank 0. <3> intbt with the higher priority occurs. the level-two interrupts occurs. the status is changed to 0 and all the interrupts are disabled. <4> rbe = 1 and rbs = 1 to select register bank 1 (only the registers used may be saved by the push instruction). <5> rbs is returned to 2, and execution returns to the main program. the status is returned to 1. reset status 0 status 0 status 1 ; rbe = 1, mbe = 0 sel ei ei ei mov mov rb2 iebt iet0 iecsi a, #9 ips, a <1> <2> intt0 <5> reti ; rbe = 0 status 1 <4> ; rbe = 1 sel rb1 sel rb2 reti status 2 <3> intbt
210 m pd750108 user's manual (4) execution of held interrupts (interrupt requests when interrupts are disabled) <1> if int0 is set when interrupts are disabled, the interrupt request flag is held. <2> when the interrupt is enabled by the ei instruction, the int0 interrupt service program starts. <3> same as <1> <4> when the held intcsi flag is enabled, the intcsi interrupt service program starts. reti ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? reset <2> ei <1> int0 <3> intcsi ei ie0 reti ei iecsi <4> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
211 chapter 6 interrupt and test functions (5) execution of held interrupts C two interrupts with lower priority occur concurrently C <1> when int0 and intt0 with the lower priority occur concurrently (during execution of the same instruction), int0, with a higher priority, is executed first. (intt0 is held.) <2> when the int0 interrupt service program has been executed, the reti instruction is executed to start the interrupt service program for intt0, which has been held. reset <2> reti <1> ei iet0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?

int0 intt0 ei ie0 ei reti
212 m pd750108 user's manual (6) executing pending interrupt C interrupt occurs during interrupt processing (intbt has higher priority and intt0 and intcsi have lower priority) C <1> when intbt with the higher priority and intt0 with the lower priority occur at the same time, the processing of the interrupt with the higher priority is started (if there is no possibility that an interrupt with the higher priority occurs while another interrupt with the higher priority is processed, di iexx is not necessary). <2> when an interrupt with the lower priority occurs while the interrupt with the higher priority is executed, the interrupt with the lower priority is kept pending. <3> when the interrupt with the higher priority has been processed, intcsi with the higher priority of the pending interrupts is executed. <4> when the processing of intcsi has been completed, the pending intt0 is processed.

reset ei ei ei mov mov iebt iet0 iecsi a, #9 ips, a intt0 reti intbt <4> reti <3> reti pop rp push rp <2> intcsi <1>
213 chapter 6 interrupt and test functions (7) enabling of level-two interrupts (enabling level-two intt0 and int0 interrupts with intcsi and int4 handled as level-one interrupts) <1> when an intcsi interrupt not allowed to be a level-two interrupt occurs, the intcsi service program starts, and status 1 is set. <2> status 0 is set by clearing ist0. intcsi and int4 not allowed to be level-two interrupts are disabled. <3> when intt0 allowed to be a level-two interrupt occurs, the level-two interrupt is executed, and status 1 is set to disable all interrupts. <4> when intt0 processing is completed, status 0 is set again. <5> intcsi and int4 which have been disabled are enabled, then control returns. reset ei iet0

ei ie0 ei iecsi status 0 status 0 status 0 status 1 status 0 status 1 <3> intt0 <2> di clr1 ist0 di iecsi di ie4 ei <4> reti ei iecsi ei ie4 reti <5> <1> intcsi ei ie4 ei ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
214 m pd750108 user's manual 6.10 test function 6.10.1 test sources the m pd750108 has two test sources. int2 provides two types of edge-detection-test inputs. table 6-5. test source test source internal/external int2 (detection of the rising edge of the signal input to the int2 pin or that of external the first falling edge of the signals input to kr0 to kr7) intw (signal from clock timer) internal 6.10.2 hardware to control test functions (1) test request flags, test enable flags test request flags (irqxxx) are set to 1 when the corresponding test requests (intxxx) are issued. clear the test request flags to 0 with the software once the test processing has been executed. test enable flags (iexxx) correspond to test request flags. the test enable flags enable the standby release signal when they are set to 1. they disables the standby release signal when they are set to 0. when both a test request flag and the corresponding test enable flag are set to 1, the standby release signal is generated. table 6-6 shows the signals which set test request flags. table 6-6. signals setting test request flags test request flag signals setting test request flags test enable flag irqw signal from the clock timer. iew irq2 detection of the rising edge of int2/p12 pin input signal or ie2 the first falling edge of the signals input to the kr0/p60 to kr7/p73 pins. the detection edge is selected with the int2 edge detection mode register (im2).
215 chapter 6 interrupt and test functions (2) int2 and key interrupt (kr0 to kr7) hardware figure 6-10 shows the configuration of int2 and kr0 to kr7. the irq2 set signal is output in either of the following edge detection modes, which is selected with the int2 edge detection mode register (im2). (a) detection of a rising edge on the int2 input pin irq2 is set when a rising edge is detected on the int2 input pin. (b) detection of a falling edge on any of the kr0 to kr7 input pins (key interrupt) one of the pins kr0 to kr7 is selected to be used for interrupt input with the int2 edge detection mode register (im2). when a falling edge of one of input signals applied to the selected pin is detected, irq2 is set. figure 6-11 shows the format of im2. im2 is set using a 4-bit manipulation instruction. when the reset signal is generated, all bits are cleared to 0, and the rising edge on int2 is specified.
216 m pd750108 user's manual figure 6-10. block diagram of the int2 and kr0 to kr7 circuits int2/p12 kr7/p73 kr6/p72 kr5/p71 kr4/p70 kr3/p63 kr2/p62 kr1/p61 kr0/p60 im2 4 input buffer internal bus selector rising edge detection circuit falling edge detection circuit int2 (irq2 set signal) im20, im21
217 chapter 6 interrupt and test functions figure 6-11. format of int2 edge detection mode register (im2) cautions 1. when the edge detection mode register is modified, test request flags may be set in some cases. so, disable test inputs before modifying the edge detection mode register. then, clear the test request flags using a clr1 instruction before enabling test inputs. 2. when a low-level signal is applied to any of the pins subjected to falling edge detection, irq2 is not set when a falling edge is detected on another pin. 0 0 im21 im20 fb6h im2 im21 0 0 1 1 im20 0 1 0 1 specifies rising edge of int2 pin input. interrupt input pin int2 kr4 - kr7 (4) kr2 - kr7 (6) kr0 - kr7 (8) specifies falling edge of any of krx pin inputs. int2 interrupt source 0 1 2 3 symbol address (1)
218 m pd750108 user's manual [memo]
219 chapter 7 standby function chapter 7 standby function the m pd750108 provides a standby function to reduce the power consumption by the system. the standby function is available in the two modes: the stop mode and halt mode. differences between these two modes are as follows: (1) stop mode in the stop mode, the main system clock oscillator is stopped, and the entire system stops. the current used by the cpu is reduced to quite a low level. in addition, the contents of data memory can be preserved with a low supply voltage of down to v dd = 1.8 v, that is, this mode is effective to retain data memory with a very low current. the wait time applied when stop mode is released by an interrupt request can be specified as 2 9 /f cc or no wait, by using a mask option. to start processing immediately upon the detection of an interrupt request, select no wait. the m pd75p0116, however, does not have a mask option and its wait time is fixed to 2 9 /f cc . if 2 9 /f cc has been selected and processing must be started immediately upon the detection of an interrupt request, select halt mode. (2) halt mode in the halt mode, the cpu clock is stopped, but the oscillation of the system clock oscillator continues. in this mode, the system uses more current than in the stop mode. however, the halt mode is suitable for starting processing immediately after an interrupt request or for intermittent operations such as watch operation. in either mode, all contents of the registers, flags, and data memory that are present immediately before the standby mode is set are preserved. in addition, the states of the output latches of the i/o ports and the states of the output buffers are also preserved, so that the states of the i/o ports are to be processed to minimize the power consumption of the entire system. cautions 1. the stop mode can be used only for the main system clock. (subsystem clock generation cannot be terminated.) the halt mode can be used for either the main system clock or the subsystem clock. 2. if the stop mode is set when main system clock f cc is used for clock timer operation, the clock stops operating. for continued operation, the clock must be changed to subsystem clock f xt before the stop mode is set. 3. a lower power consumption and lower-voltage operation are enabled by switching standby modes or switching cpu and system clocks. however, a switching time as described in section 5.2.3 is required before operation is started with a new clock after the clock is selected with the control register. for this reason, when the clock switching function is used together with a standby mode, the standby mode must be set after a time needed for switching elapses. 4. configure i/o ports for minimum power consumption in the stand by mode. be sure to connect signals which are high or low to input ports. 7
220 m pd750108 user's manual 7.1 setting of standby modes and operation status table 7-1. operation statuses in the standby mode notes 1. operation is possible only when the main system clock operates. 2. operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register (im0) (when im02 = 1). a stop instruction is used to set the stop mode, and a halt instruction is used to set the halt mode. (a stop instruction sets bit 3 of pcc, and a halt instruction sets bit 2 of pcc.) stop instruction or halt instruction must always be followed by an nop instruction. when changing a cpu operation clock pulse with the low-order two bits of pcc, a time lag may occur from the time when pcc is rewritten as shown in table 5-5 to the time when the cpu clock signal is changed. when changing an operation clock pulse before the standby mode or a cpu clock signal after the standby mode is released, it is necessary to rewrite pcc and set the standby mode after as many machine cycles as required to change the cpu clock pulse have elapsed. in a standby mode, the contents of all registers and data memory that are stopped during the standby mode, including general registers, flags, mode registers, and output latches, are retained. halt mode halt instruction can be set either with the main system clock or the subsystem clock only the cpu clock f stops its operation (oscillation continues) can operate only at main system clock oscillation. (irqbt is set at reference time intervals.) can operate only when external sck input is selected as the serial clock or at main system clock oscillation. can operate only when ti0 pin input is specified as the count clock or at main system clock oscillation. can operate note 1 can operate stop mode stop instruction can be set only when operating on the main system clock the main system clock stops its operation does not operate can operate only when the external sck input is selected for the serial clock can operate only when the ti0 pin input is selected for the count clock does not operate can operate when f xt is selected as the count clock int1, int2, and int4 can operate. only int0 cannot operate. note 2 does not operate operation status item an interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a reset signal mode instruction for setting system clock for setting clock oscillator basic interval timer/watchdog timer serial interface timer/event counter timer counter clock timer external interrupt cpu release signal
221 chapter 7 standby function caution reset all the interrupt request flags before setting the standby mode. if an interrupt source whose interrupt request flag and interrupt enable flag are both set exists, the initiated standby mode is released immediately after it is set (see figure 6-1). when the stop mode is set, however, the m pd750108 enters the halt mode immediately after the stop instruction is executed, then returns to the operation mode after the specified wait time note has elapsed. note either of the following can be selected by using a mask option: ?2 9 /f cc (256 m s at 2 mhz, 512 m s at 1 mhz) no wait the m pd75p0116, however, does not have a mask option. its wait time is fixed to 2 9 /f cc . 7.2 release of the standby modes the stop mode and halt mode are released by a reset signal or the generation of an interrupt request signal that is enabled with the interrupt enable flag. figure 7-1 shows how the stop and halt modes are released. figure 7-1. standby mode release operation (1/2) (a) release of the stop mode by reset signal (b) release of the stop mode by the occurrence of an interrupt stop instruction standby release signal clock operating mode stop mode halt mode operating mode no oscillation oscillation oscillation wait note 2 stop instruction wait reset signal clock operating mode stop mode halt mode operating mode no oscillation oscillation oscillation note 1
222 m pd750108 user's manual notes 1. 56/f cc (28 m s at 2 mhz, 56 m s at 1 mhz) 2. either of the following can be selected by using a mask option: ?2 9 /f cc (256 m s at 2 mhz, 512 m s at 1 mhz) no wait the m pd75p0116, however, does not have a mask option. its wait time is fixed to 2 9 /f cc . remark the dashed line indicates the case where the interrupt request that releases the standby mode is accepted. figure 7-1. standby mode release operation (2/2) (c) release of the halt mode by reset signal (d) release of the halt mode by the occurrence of an interrupt note 56/f cc (28 m s at 2 mhz, 56 m s at 1 mhz) remark the dashed line indicates the case where the interrupt request that releases the standby mode is accepted. halt instruction reset signal clock operating mode halt mode operating mode oscillation wait note halt instruction standby release signal clock halt mode operating mode oscillation operating mode
223 chapter 7 standby function 7.3 operation after a standby mode is released (1) if a standby mode is released by a reset signal, normal reset operation is performed. (2) if a standby mode is released by the occurrence of an interrupt request, the contents of the interrupt master enable flag (ime) determines whether to perform a vectored interrupt when the cpu resumes instruction execution. (a) when ime = 0 if a standby mode is released, execution restarts with the instruction immediately following the instruction used to set the standby mode. the interrupt request flag is held. (b) when ime = 1 if a standby mode is released, a vectored interrupt is executed after the two instructions are executed. however, if the standby mode is released by int2 or intw (testable input), no vectored interrupt occurs, and the same processing as (a) above is performed. 7.4 selection of a mask option for the standby function of the m pd750108, the wait time applied when stop mode is released by an interrupt can be set to either of the following by using a mask option: <1> 2 9 /f cc (256 m s at 2 mhz, 512 m s at 1 mhz) <2> no wait the m pd75p0116, however, does not have a mask option. its wait time is fixed to 2 9 /f cc .
224 m pd750108 user's manual 7.5 applications of the standby modes when the standby modes are used, the following steps are used. <1> detect a standby mode setting factor such as power removal on an interrupt input or port input. (int4 is useful for power removal detection.) <2> configure i/o ports for minimum current drain. <3> specify interrupts for releasing a standby mode. (int4 is useful. all interrupt enable flags not used for release are to be cleared.) <4> specify an operation to be performed after release. (ime is to be manipulated according to whether interrupt processing is performed or not.) <5> specify a cpu clock to be used after release. (if the cpu clock is changed, required machine cycles must elapse before the standby mode is set.) <6> select a wait time to be used when a standby mode is released. <7> set a standby mode using a stop or halt instruction. a standby mode when combined with the system clock switch function enables a lower power consumption and lower-voltage operation. (1) application of the stop mode (at f cc = 1 mhz) ? the stop mode is set on the falling edge of int4, and is released on the rising edge of int4. (intbt is not used.) ? all i/o ports have a high impedance. ? the int0 and intt0 interrupts are used for the program, but are not used to release the stop mode. ? after the stop mode is released, interrupts are enabled. ? after the stop mode is released, operation is started using the lowest-speed cpu clock. ? the wait time applied when the stop mode is released is set to 512 m s by using a mask option. after the stop mode is released, another wait time of 32.8 ms is used for stable power supply operation. the p00/int4 pin is checked twice to remove chattering.
225 chapter 7 standby function (int4 service program, mbe = 0) vsub4: skt port0.0 ; p00 = 1? br pdown ; power-down mov a,#1101b mov btm,a ; wait time = 32.8 ms wait: skt irqbt ; wait for 512 m s. br wait skt port0.0 ; chattering check br pdown mov a,#0011b mov pcc,a ; set high-speed mode. mov xa.#xxh ; set port mode register. mov pmgm,xa ei ie0 ei iet0 reti pdown: mov a,#0 ; lowest-speed mode mov pcc,a mov xa,#00h mov pmga,xa ; i/o port high impedance mov pmgb,xa di ie0 ; disable int0 and intt0 di iet0 stop ; set stop mode. nop reti * int4 int4 512 s 32.8 ms halt mode (wait) low-speed operation stop mode operating mode stop instruction v dd 0 v p00/int4 cpu operation voltage on v dd high-speed operation
226 m pd750108 user's manual (2) application of the halt mode (at f cc = 1 mhz) ? the main system clock is switched to the subsystem clock on the falling edge of int4. ? the oscillation of the main system clock is stopped, and halt mode is set. ? in the standby mode, intermittent operation is performed at intervals of 0.5 s. ? the subsystem clock is switched back to the main system clock on the rising edge of int4. ? intbt is not used. ? after the stop mode is released, another wait time of 32.8 ms is used for stable power supply operation. the p00/int4 pin is checked twice to remove chattering. int4 int4 32.8 ms operating mode (low-speed) intermittent operation (halt mode + low-speed operation) operating mode v dd 0 v p00/int4 cpu operation voltage on v dd operating mode (high-speed) *
227 chapter 7 standby function (initialization) mov a,#0011b mov pcc,a ; high-speed mode mov xa,#05 mov wm,xa ; subsystem clock ei ie4 ei iew ei ; enable interrupt (main routine) skt port0.0 ; power normal? halt ; power-down mode nop ; power normal? sktclr irqw ; flag set for 0.5 second? br main ; no call watch ; clock subroutine main: . . . . . . . . . . (int4 service routine) vint4: skt port0.0 ; power normal? mbe = 0 br pdown clr1 scc.3 ; start main system clock oscillation mov a,#0dh mov btm,a wait1: skt irqbt ; wait for 32.8 ms br wait1 skt port0.0 ; chattering check br pdown clr1 scc.0 ; switch to main system clock reti pdown: set1 scc.0 ; switch to subsystem clock mov a,#0ah wait2: incs a ; wait for 15 machine cycles br wait2 set1 scc.3 ; stop main system clock oscillation reti caution before the system clock is changed from the main system clock to the subsystem clock, a wait time sufficient for stable subsystem clock generation is required.
228 m pd750108 user's manual [memo]
229 chapter 8 reset function chapter 8 reset function the m pd750108 is reset with the external reset signal (reset) or the reset signal received from the basic interval timer/watchdog timer. when either reset signal is input, the internal reset signal is generated. figure 8-1 shows the configuration of the reset circuit. figure 8-1. configuration of reset functions when the reset signal is generated, all hardware is initialized as indicated in table 8-1. figure 8-2 shows the reset operation timing. figure 8-2. reset operation by generation of reset signal note 56/f cc (28 m s at 2 mhz, 56 m s at 1 mhz). 8 wdtm reset internal reset signal reset signal from basic interval timer/watchdog timer internal bus reset signal is generated operating mode or standby mode halt mode operating mode internal reset operation wait note
230 m pd750108 user's manual table 8-1. status of the hardware after a reset (1/2) program counter (pc) psw stack pointer (sp) stack bank selection register (sbs) data memory (ram) general registers (x, a, h, l, d, e, b, c) bank selection register (mbs, rbs) basic interval timer/watch- dog timer timer/ event counter timer counter clock timer serial interface m PD750104 m pd750106, m pd750108 m pd75p0116 generation of a reset signal in a standby mode 4 low-order bits at address 0000h in program memory are set in pc bits 11 to 8, and the data at address 0001h are set in pc bits 7 to 0. 5 low-order bits at address 0000h in program memory are set in pc bits 12 to 8, and the data at address 0001h are set in pc bits 7 to 0. 6 low-order bits at address 0000h in program memory are set in pc bits 13 to 8, and the data at address 0001h are set in pc bits 7 to 0. held 0 0 bit 6 at address 0000h in program memory is set in rbe, and bit 7 is set in mbe. undefined 1000b held held 0, 0 undefined 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 held 0 0 held carry flag (cy) skip flags (sk0 to sk2) interrupt status flags (ist0, ist1) bank enable flags (mbe, rbe) counter (bt) mode register (btm) watchdog timer enable flag (wdtm) counter (t0) modulo register (tmod0) mode register (tm0) toe0, tout flip-flop counter (t1) modulo registers (tmod1) mode register (tm1) toe1, tout flip-flop mode register (wm) shift register (sio) operation mode register (csim) sbi control register (sbic) slave address register (sva) generation of a reset signal during operation 4 low-order bits at address 0000h in program memory are set in pc bits 11 to 8, and the data at address 0001h are set in pc bits 7 to 0. 5 low-order bits at address 0000h in program memory are set in pc bits 12 to 8, and the data at address 0001h are set in pc bits 7 to 0. 6 low-order bits at address 0000h in program memory are set in pc bits 13 to 8, and the data at address 0001h are set in pc bits 7 to 0. undefined 0 0 bit 6 at address 0000h in program memory is set in rbe, and bit 7 is set in mbe. undefined 1000b undefined undefined 0, 0 undefined 0 0 0 ffh 0 0, 0 0 ffh 0 0, 0 0 undefined 0 0 undefined hardware *
231 chapter 8 reset function table 8-1. statuses of the hardware after a reset (2/2) processor clock control register (pcc) system clock control register (scc) clock output mode register (clom) interrupt request flag (irqxxx) interrupt enable flag (iexxx) priority selection register (ips) int0, int1, and int2 mode registers (im0, im1, im2) output buffer output latch i/o mode registers (pmga, pmgb, pmgc) pull-up resistor specification register (poga, pogb) hardware generation of a reset signal during operation 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 undefined sub-oscillator control register (sos) clock generator, clock output circuit interrupt digital ports generation of a reset signal in a standby mode 0 0 0 0 reset (0) 0 0 0, 0, 0 off clear (0) 0 0 held bit sequential buffers (bsb0 to bsb3)
232 m pd750108 user's manual [memo]
233 chapter 9 writing to and verifying program memory (prom) chapter 9 writing to and verifying program memory (prom) the program memory in the m pd75p0116 consists of a one-time prom (16384 x 8 bits). writing to and verifying the contents of the one-time prom is accomplished by using the pins shown in the table below. note that address inputs are not used; instead, the address is updated using the clock input from the cl1 pin. pin name function v pp voltage is applied to this pin when writing to the program memory or verifying its contents (normally v dd electric potential). cl1, cl2 an address update clock, used when writing to program memory or verifying its contents, is input to the cl1 pin. leave the cl2 pin open. md0 to md3 operation mode selection pins used when writing to the program memory or verifying its contents. d0/p40 to d3/p43 i/o pins for 8-bit data used when writing to the program memory or verifying (low-order four bits) its contents. d4/p50 to d7/p53 (high-order four bits) v dd power voltage is applied to this pin. during normal operation, 1.8 to 5.5 v should be applied; +6 v should be applied when writing to the program memory or verifying its contents. cautions 1. the m pd75p0116cu/gb does not have an erasure window, so the erasing with ultraviolet radiation cannot be performed. 2. handle the pins not used for writing to or verifying the program memory, as follows: ? pins other than xt2: connect these pins to v ss through pull-down resistors. ? xt2 pin: open 9
234 m pd750108 user's manual 9.1 operating modes when writing to and verifying the program memory if +6 v is applied to the v dd pin and +12.5 v is applied to the v pp pin, the m pd75p0116 enters program memory write/verify mode. the specific operating mode is then selected by the setting of the md0 through md3 pins as listed in the table below. operating mode specification operating mode v pp v dd md0 md1 md2 md3 +12.5 v +6 v h l h l program memory address clear mode l h h h write mode l l h h verify mode h x h h program inhibit mode remark x indicates l or h. 9.2 writing to the program memory the procedure for writing to program memory is described below; high-speed write is possible. (1) pull low all unused pins to v ss by means of resistors. bring cl1 to low level. (2) apply 5 v to v dd and to v pp . (3) wait 10 m s. (4) select program memory address clear mode. (5) apply 6 v to v dd and 12.5 v to v pp . (6) select write mode for 1 ms duration and write data. (7) select verify mode. if write is successful, proceed to step (8). if write fails, repeat steps (6) and (7). (8) perform additional write for (number of repetitions of steps (6) and (7)) x 1 ms duration. (9) increment the program memory address by inputting four pulses on the cl1 pin. (10) repeat steps (6) to (9) until the last address is reached. (11) select program memory address clear mode. (12) apply 5 v to v dd and to v pp . (13) turn the power off. *
235 chapter 9 writing to and verifying program memory (prom) the timing for steps (2) to (9) is shown below. v pp v dd v pp v dd+1 v dd v dd cl1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 write verify additional write address increment repeat x times data input data output data input
236 m pd750108 user's manual 9.3 reading the program memory the procedure for reading the contents of program memory is described below. the read is performed in the verify mode. (1) pull low all unused pins to v ss by means of resistors. bring cl1 to low level. (2) apply 5 v to v dd and v pp . (3) wait 10 m s. (4) select program memory address clear mode. (5) apply 6 v to v dd and 12.5 v to v pp . (6) select verify mode. data is output sequentially one address at a time for each cycle of four clock pulses appearing on the cl1 pin. (7) select program memory address clear mode. (8) apply 5 v to v dd and to v pp . (9) turn the power off. the timing for steps (2) to (7) is shown below. * v pp v dd v pp v dd+1 v dd v dd cl1 d0/p40-d3/p43 d4/p50-d7/p53 md0/p30 md1/p31 md2/p32 md3/p33 data output data output l
237 chapter 9 writing to and verifying program memory (prom) 9.4 screening of one-time prom because of its structure, it is difficult for nec to completely test the one-time prom product before shipment. it is therefore recommended that screening be performed to verify the prom contents after the necessary data has been written to the prom and the product has been stored under the following conditions. storage temperature storage time 125 c 24 hours
238 m pd750108 user's manual [memo]
239 chapter 10 mask option chapter 10 mask option 10.1 pin the pins of the m pd750108 have the following mask options: table 10-1. selecting mask option of pin pin mask option p40-p43 pull-up resistor can be connected in 1-bit units. p50-p53 p40 through p43 (port 4) or p50 through p53 (port 5) can be connected with pull-up resistors by mask option. the mask option can be specified in 1-bit units. if the pull-up resistor is connected by mask option, port 4 or 5 goes high on reset. if the pull-up resistor is not connected, the port goes into a high-impedance state on reset. pull-up resistors, specified with the mask option, are not connected to the m pd75p0116. 10.2 mask option of standby function the standby function of the m pd750108 allows you to select wait time by using a mask option. the wait time is required for the cpu to return to the normal operation mode after stop mode has been released by an interrupt (for details, see section 7.2 ). the wait time can be set to either of the following: <1> 2 9 /f cc (256 m s at 2 mhz, 512 m s at 1 mhz) <2> no wait the m pd75p0116 does not have a mask option and its wait time is fixed to 2 9 /f cc . 10
240 m pd750108 user's manual 10.3 mask option for feedback resistor of subsystem clock for the subsystem clock of the m pd750108, whether to enable the feedback resistor is selected by the mask option. <1> enable the feedback resistor (switches on or off by software). <2> disable the feedback resistor (cuts by hardware). to use the feedback resistor after selecting <1> , turn the feedback resistor on by setting sos.0 to 0 (for details, see (6) in section 5.2.2 ). select <1> to use the subsystem clock. for the m pd75p0116, the mask option need not be set; use of the feedback resistor is factory-set.
241 chapter 11 instruction set chapter 11 instruction set the instruction set of the m pd750108 is an improved and extended version of the 75x series instruction set. this instruction set takes over the instruction set of the 75x series, having the following features: (1) bit manipulation instructions allowing a wide variety of applications (2) efficient 4-bit manipulation instructions (3) eight-bit instructions comparable to 8-bit microcontrollers (4) geti instruction for reducing program sizes (5) string-effect instructions and number system conversion instructions for increased program efficiency (6) table reference instructions suitable for successive references (7) 1-byte relative branch instructions (8) nec standard mnemonics designed for clarity and readability see section 3.2 for the addressing modes applicable to data memory manipulation and register banks used for instruction execution. 11.1 unique instructions this section outlines the unique instructions among the m pd750108 instruction set. 11.1.1 geti instruction the geti instruction converts any of the following instructions to a 1-byte instruction: (a) subroutine call instruction for the entire space (b) branch instruction for the entire space (c) arbitrary 2-byte instruction operating with two machine cycles (except the brcb and callf instructions) (d) a combination of two 1-byte instructions the geti instruction references the table located at addresses 0020h to 007fh in program memory, and executes referenced 2-byte data as an instruction of (a), (b), (c), or (d) above. this means that 48 instructions consisting of (a) to (d) can be converted to 1-byte instructions. thus the geti instruction can be used to convert frequently used instructions of (a) to (d) to 1-byte instructions to reduce the number of program bytes significantly. 11
242 m pd750108 user's manual 11.1.2 bit manipulation instruction the m pd750108 has reinforced bit test, bit transfer, and bit boolean (and, or, and xor) instruction, in addition to the ordinary bit manipulation (set and clear) instructions. the bit to be manipulated is specified in the bit manipulation addressing mode. three types of bit manipulation addressing modes can be used. the bits manipulated in each addressing mode are shown in table 11-1. table 11-1. types of bit manipulation addressing modes and specification range addressing peripheral hardware that can be addressing range of bit that can be manipulated manipulated fmem. bit rbe, mbe, ist1, ist0, scc, fb0h-fbfh iexxx, irqxxx port0-8 ff0h-fffh pmem. @l bsb0-3, port0-8 fc0h-fffh @h+mem. bit all peripheral hardware units that can be all bits of memory bank specified by mb manipulated bitwise that can be manipulated bitwise remarks 1. xxx: 0, 1, 2, 4, bt, t0, t1, w, csi 2. mb = mbe ? mbs 11.1.3 string-effect instructions with the m pd750108, two types of string-effect instructions are available. (a) mov a,#n4 or mov xa,#n8 (b) mov hl,#n8 "string effect" means the locating of these two types of instructions at contiguous addresses. example a0: mov a,#0 a1: mov a,#1 xa7: mov xa,#07 when string-effect instructions are arranged as in this example, if execution starts at address a0, the following two instructions are replaced with an nop instruction. if execution starts at address a1, the following one instruction is replaced with an nop instruction. that is, only the instruction first executed is valid, and any following instructions are processed as an nop instruction. by using string-effect instructions, a constant can be set in an accumulator (the a register or the xa register pair) or data pointer (the hl register pair) more efficiently.
243 chapter 11 instruction set 11.1.4 number system conversion instructions an application may need to convert the result of a 4-bit data addition or subtraction (performed in binary) to a decimal number. a time-related application may require sexagesimal conversion. for this reason, the instruction set of the m pd750108 contains number system conversion instructions for converting the result of a 4-bit data addition or subtraction to a number in an arbitrary number system. (a) number system conversion for addition let m be a desired number system after conversion. the following combination of instructions adds the contents of an accumulator to data in memory (hl), then converts the result of the addition to number system m. adds a,#16 C m addc a,@hl ; a, cy 244 m pd750108 user's manual 11.1.5 skip instructions and the number of machine cycles required for a skip the instruction set of the m pd750108 is designed to organize a program by testing a condition with the skip function. when a skip instruction satisfies the skip condition, the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction. a skip requires the following number of machine cycles: (a) when the instruction (to be skipped) immediately following the skip instruction is a 3-byte instruction (that is, the br !addr, bra !addr1, call !addr, or calla !addr1 instruction): 2 machine cycles (b) when the instruction (to be skipped) immediately following the skip instruction is an instruction other than the instructions described in (a) above: 1 machine cycle
245 chapter 11 instruction set 11.2 instruction set and operation (1) operand identifier and description the operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction. (refer to ra75x assembler package users manual: language (eeu-1343 ) for detailed information.) when there are multiple descriptions for an identifier, one item is to be selected. the uppercase letters and + and C signs are keywords, which must be coded as they appear. for immediate data, a proper numeric value or label must be coded. the abbreviations for register flags shown in figure 3-7 can be coded as labels in place of mem, fmem, pmem, and bit. (however, not all labels can be coded for the fmem and pmem. for details, see table 3-1 and figure 3-7 ) representation format description method reg x, a, b, c, d, e, h, l reg1 x, b, c, d, e, h, l rp xa, bc, de, hl rp1 bc, de, hl rp2 bc, de rp xa, bc, de, hl, xa, bc, de, hl rp1 bc, de, hl, xa, bc, de, hl rpa hl, hl+, hlC, de, dl rpa1 de,dl n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label note bit 2-bit immediate data or label fmem fb0h-fbfh and ff0h-fffh immediate data or label pmem fc0h-fffh immediate data or label addr, 0000h-0fffh immediate data or label ( m PD750104) addr1(for mkii mode only) 0000h-17ffh immediate data or label ( m pd750106) 0000h-1fffh immediate data or label ( m pd750108) 0000h-3fffh immediate data or label ( m pd75p0116) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20h-7fh immediate data (bit 0 = 0) or label portn port0-port8 iexxx iebt, iet0, iet1, ie0-ie2, ie4, iecsi, iew rbn rb0-rb3 mbn mb0, mb1, mb15 note for mem, only even addresses can be coded for 8-bit data processing.
246 m pd750108 user's manual (2) legend a: a register; 4-bit accumulator b: b register c: c register d: d register e: e register h: h register l: l register x: x register xa: register pair (xa), 8-bit accumulator bc: register pair (bc) de: register pair (de) hl: register pair (hl) xa: extended register pair (xa) bc: extended register pair (bc) de: extended register pair (de) hl: extended register pair (hl) pc: program counter sp: stack pointer cy: carry flag, bit accumulator psw: program status word mbe: memory bank enable flag rbe: register bank enable flag portn: port n (n = 0 to 8) ime: interrupt master enable flag ips: interrupt priority specification register iexxx: interrupt enable flag rbs: register bank select register mbs: memory bank select register pcc: processor clock control register .: address/bit delimiter (xx): contents addressed by xx xxh: hexadecimal data
247 chapter 11 instruction set (3) explanation of symbols used for the addressing area column remarks 1. mb represents an accessible memory bank. 2. for * 2, mb = 0 regardless of the setting of mbe and mbs. 3. for * 4 and * 5, mb = 15 regardless of the setting of mbe and mbs. 4. each of * 6 to * 11 indicates an addressable area. * 1 mb = mbe mbs (mbs = 0, 1, 15) * 2 mb = 0 * 3 mbe = 0 : mb = 0 * 4 mb = 15, fmem = fb0h - fbfh, * 5 mb = 15, pmem = fc0h - fffh * 6 addr, addr1 = 0000h - 0fffh * 7 addr , addr1 = (current pc) C 15 to (current pc) C 1 * 8 caddr = 0000h - 0fffh caddr = 0000h - 0fffh (pc 12 = 0) or * 9 faddr = 0000h - 07ffh * 10 taddr = 0020h - 007fh * 11 for mkii mode only addr1 = data memory addressing program memory addressing PD750104 pd750106 pd750108 pd75p0116 PD750104 pd750106 pd750108 pd75p0116 addr, addr1 = 0000h - 17ffh addr, addr1 = 0000h - 1fffh addr, addr1 = 0000h - 3fffh (000h - 07fh) (f80h - fffh) (mbs =0, 1, 15) 0000h - 0fffh ( PD750104) 0000h - 17ffh ( pd750106) 0000h - 1fffh ( pd750108) 0000h - 3fffh ( pd75p0116) 1000h - 1fffh (pc 12 = 1) 0000h - 0fffh (pc 13 , pc 12 = 00b) or 1000h - 1fffh (pc 13 , pc 12 = 01b) or 2000h - 2fffh (pc 13 , pc 12 = 10b) or 3000h - 3fffh (pc 13 , pc 12 = 11b) caddr = 1000h - 17ffh (pc 12 = 1) caddr = 0000h - 0fffh (pc 12 = 0) or (current pc) + 2 to (current pc) + 16 ff0h - fffh mb = 15 mbe = 1 : mb = mbs
248 m pd750108 user's manual (4) explanation of the machine cycle column s represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation. s assumes one of the following values: ? when no skip operation is performed: s = 0 ? when a 1-byte instruction or 2-byte instruction is skipped: s = 1 ? when a 3-byte instruction note is skipped: s = 2 note 3-byte instruction: br !addr, bra !addr1, call !addr, and calla !addr1 instructions caution the geti instruction is skipped in one machine cycle. one machine cycle is equal to one cycle (t cy ) of the cpu clock ( f ), and four different machine cycles are available for selection according to the pcc setting. (see figure 5-12 .)
249 chapter 11 instruction set in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area mov a,#n4 1 1 a (hl) * 1 a,@hl+ 1 2+s a (hl), then l <- l+1 * 1 l=0 a,@hlC 1 2+s a (hl), then l <- lC1 * 1 l=fh a,@rpa1 1 1 a (rpa1) * 2 xa,@hl 2 2 xa (hl) * 1 a,mem 2 2 a (mem) * 3 xa,mem 2 2 xa (mem) * 3 a,reg1 1 1 a reg1 xa,rp 2 2 xa rp transfer
250 m pd750108 user's manual in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area movt xa,@pcde 1 3 ? m PD750104 xa PD750104 xa PD750104. only the lsb is valid in register b in the m pd750106 and m pd750108. only the low-order two bits are valid in the m pd75p0116. arithmetic/logical table reference bit transfer
251 chapter 11 instruction set in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area and a,#n4 2 2 a 252 m pd750108 user's manual in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area set1 mem.bit 2 2 (mem.bit) 253 chapter 11 instruction set branch in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area br addr ? m PD750104 * 6 pc 11-0 PD750104 * 11 pc 11-0 254 m pd750108 user's manual branch notes 1. set register b to 0. 2. only the lsb is valid in register b. 3. only the low-order two bits are valid in register b. in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area br !addr 3 3 ? m PD750104 * 6 pc 11-0 PD750104 * 7 pc 11-0 PD750104 * 7 pc 11-0 PD750104 pc 11-0 PD750104 pc 11-0 PD750104 * 11 pc 11-0 255 chapter 11 instruction set in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area br bcxa 2 3 ? m PD750104 * 11 pc 11-0 PD750104 * 11 pc 11-0 PD750104 * 8 pc 11-0 PD750104 * 11 (spC2) 256 m pd750108 user's manual in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area call note !addr 3 3 ? m PD750104 * 6 (spC3) PD750104 (spC2) PD750104 * 9 (spC3) 257 chapter 11 instruction set in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area callf note !faddr 2 3 ? m PD750104 * 9 (spC2) C> x, x, mbe,rbe (spC6)(spC3)(spC4) x, x, mbe,rbe (spC6)(spC3)(spC4) PD750104 pc 11-0 PD750104 x, x, mbe, rbe 258 m pd750108 user's manual subroutine stack control in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area rets note 1 3+s ? m PD750104 unconditionally mbe, rbe, 0, 0 PD750104 0, 0, 0, 0 PD750104 mbe, rbe, 0, 0 259 chapter 11 instruction set in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area reti note 1 13? m PD750104 0, 0, 0, 0 260 m pd750108 user's manual special in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area sel rbn 2 2 rbs PD750104 * 10 when the tbr instruction is used pc 11-0 261 chapter 11 instruction set special in- mne- number machine address- struc- monic operand of cycle operation ing skip condition tion bytes area geti notes1, 2 taddr 1 3 ? m PD750104 * 10 when the tbr instruction is used pc 11-0 262 m pd750108 user's manual 11.3 instruction codes of each instruction (1) explanations of the symbols for the instruction codes i n : immediate data for n4 or n8 d n : immediate data for mem b n : immediate data for bit n n : immediate data for n or iexxx t n : immediate data for taddr x 1/2 a n : immediate data for the address (2 to 16) relative to branch destination address minus one s n : immediate data for the ones complement of the address (15 to 1) relative to the branch destination address reg r 2 r 1 r 0 reg 000 a 001 x 010 l 011 h 100 e 101 d 110 c 111 b reg1 rp' p 2 p 1 p 0 reg-pair 000 xa 0 0 1 xa' 010 hl 0 1 1 hl' 100 de 1 0 1 de' 110 bc 1 1 1 bc' rp'1 q 2 q 1 q 0 addressing 0 0 0 @hl 0 1 0 @hl+ 0 1 1 @hlC 1 0 0 @de 1 0 1 @dl @rpa rp2 p 2 p 1 reg-pair 00 xa 01 hl 10 de 11 bc rp1 rp n 5 n 2 n 1 000 001 110 010 010 011 011 100 n 0 0 0 0 0 1 0 1 0 iexxx iebt iew iet1 iet0 iecsi ie0 ie2 ie4 1 1 1 0 ie1 @rpa1
263 chapter 11 instruction set (2) bit manipulation addressing instruction codes * 1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit, pmem.@l, and @h+mem.bit. the table below lists the second byte * 2 of an instruction code corresponding to the above addressing. * 1 second byte of instruction code accessible bits fmem.bit 1 0 b 1 b 0 f 3 f 2 f 1 f 0 fb0h-fbfh manipulatable bits 11b 1 b 0 f 3 f 2 f 1 f 0 ff0h-fffh manipulatable bits pmem.@l 0 1 0 0 g 3 g 2 g 1 g 0 fc0h-fffh manipulatable bits @h+mem.bit 0 0 b 1 b 0 d 3 d 2 d 1 d 0 manipulatable bits of accessible memory bank b n : immediate data for bit f n : immediate data for fmem (low-order four bits of address) g n : immediate data for pmem (bits 2 to 5 of address) d n : immediate data for mem (low-order four bits of address)
264 m pd750108 user's manual instruction mne- operand instruction code monic b 1 b 2 b 3 transfer mov a,#n4 0111i 3 i 2 i 1 i 0 reg1,#n4 10011010 i 3 i 2 i 1 i 0 1r 2 r 1 r 0 rp,#n8 10001p 2 p 1 1i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a,@rpa1 11100q 2 q 1 q 0 xa,@hl 10101010 00011000 @hl,a 11101000 @hl,xa 10101010 00010000 a,mem 10100011 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa,mem 10100010 d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 mem,a 10010011 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 mem,xa 10010010 d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a,reg 10011001 01111r 2 r 1 r 0 xa,rp 10101010 01011p 2 p 1 p 0 reg1,a 10011001 01110r 2 r 1 r 0 rp1,xa 10101010 01010p 2 p 1 p 0 xch a,@rpa1 11101q 2 q 1 q 0 xa,@hl 10101010 00010001 a,mem 10110011 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 xa,mem 10110010 d 7 d 6 d 5 d 4 d 3 d 2 d 1 0 a,reg1 11011r 2 r 1 r 0 xa,rp 10101010 01000p 2 p 1 p 0 table movt xa,@pcde 11010100 reference xa,@pcxa 11010000 xa,@bcxa 11010001 xa,@bcde 11010101 bit mov1 cy, * 1 10111101 * 2 transfer * 1 ,cy 10011011 * 2
265 chapter 11 instruction set instruction mne- operand instruction code monic b 1 b 2 b 3 arithmetic/ adds a,#n4 0110i 3 i 2 i 1 i 0 logical xa,#n8 10111001 i 7 i 6 i 5 i 4 i 3 i 2 i 1 i 0 a,@hl 11010010 xa,rp 10101010 11001p 2 p 1 p 0 rp1,xa 10101010 11000p 2 p 1 p 0 addc a,@hl 10101001 xa,rp 10101010 11011p 2 p 1 p 0 rp1,xa 10101010 11010p 2 p 1 p 0 subs a,@hl 10101000 xa,rp 10101010 11101p 2 p 1 p 0 rp1,xa 10101010 11100p 2 p 1 p 0 subc a,@hl 10111000 xa,rp 10101010 11111p 2 p 1 p 0 rp1,xa 10101010 11110p 2 p 1 p 0 and a,#n4 10011001 0011i 3 i 2 i 1 i 0 a,@hl 10010000 xa,rp 10101010 10011p 2 p 1 p 0 rp1,xa 10101010 10010p 2 p 1 p 0 or a,#n4 10011001 0100i 3 i 2 i 1 i 0 a,@hl 10100000 xa,rp 10101010 10101p 2 p 1 p 0 rp1,xa 10101010 10100p 2 p 1 p 0 xor a,#n4 10011001 0101i 3 i 2 i 1 i 0 a,@hl 10110000 xa,rp 10101010 10111p 2 p 1 p 0 rp1,xa 10101010 10110p 2 p 1 p 0 accumulator rorc a 10011000 manipulation not a 10011001 01011111
266 m pd750108 user's manual instruction mne- operand instruction code monic b 1 b 2 b 3 increment/ incs reg 11000r 2 r 1 r 0 decrement rp1 10001p 2 p 1 0 @hl 10011001 00000010 mem 10000010 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 decs reg 11001r 2 r 1 r 0 rp 10101010 01101p 2 p 1 p 0 comparison ske reg,#n4 10011010 i 3 i 2 i 1 i 0 0r 2 r 1 r 0 @hl,#n4 10011001 0110i 3 i 2 i 1 i 0 a,@hl 10000000 xa,@hl 10101010 00011001 a,reg 10011001 00001r 2 r 1 r 0 xa,rp 10101010 01001p 2 p 1 p 0 carry flag set1 cy 11100111 manipu- clr1 cy 11100110 lation skt cy 11010111 not1 cy 11010110 memory set1 mem.bit 1 0 b 1 b 0 0101 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 bit * 1 10011101 * 2 manipu- clr1 mem.bit 1 0 b 1 b 0 0100 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 lation * 1 10011100 * 2 skt mem.bit 1 0 b 1 b 0 0111 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10111111 * 2 skf mem.bit 1 0 b 1 b 0 0110 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 * 1 10111110 * 2 sktclr * 1 10011111 * 2 and1 cy, * 1 10101100 * 2 or1 cy, * 1 10101110 * 2 xor1 cy, * 1 10111100 * 2
267 chapter 11 instruction set instruction mne- operand instruction code monic b 1 b 2 b 3 branch br !addr 10101011 00 addr $addr1 0000a 3 a 2 a 1 a 0 (+16) to (+2) (C1) to (C15) 1111s 3 s 2 s 1 s 0 pcde 10011001 00000100 pcxa 10011001 00000000 bcde 00000101 bcxa 10011001 00000001 bra !addr1 10111010 0 addr1 brcb !caddr 0101 caddr sub- call !addr 10101011 01 addr routine calla !addr1 10111011 0 addr1 stack callf !faddr 01000 faddr control ret 11101110 rets 11100000 reti 11101111 push rp 01001p 2 p 1 1 bs 10011001 00000111 pop rp 01001p 2 p 1 0 bs 10011001 00000110 i/o in a,portn 10100011 1111n 3 n 2 n 1 n 0 xa,portn 10100010 1111n 3 n 2 n 1 n 0 out portn,a 10010011 1111n 3 n 2 n 1 n 0 portn,xa 10010010 1111n 3 n 2 n 1 n 0 interrupt ei 10011101 10110010 control iexxx 10011101 10n 5 11n 2 n 1 n 0 di 10011100 10110010 iexxx 10011100 10n 5 11n 2 n 1 n 0 cpu halt 10011101 10100011 control stop 10011101 10110011 nop 01100000 special sel rbn 10011001 001000n 1 n 0 mbn 10011001 0001n 3 n 2 n 1 n 0 geti taddr 0 0 t 5 t 4 t 3 t 2 t 1 t 0
268 m pd750108 user's manual 11.4 functions and applications of the instructions this section explains functions and applications of the instructions. for the m PD750104, m pd750106, m pd750108, and m pd75p0116, usable instructions and their functions in mk i mode are different from those in mk ii mode. read the following explanation. how to read can be used in both mk i mode and mk ii mode for the m PD750104, m pd750106, m pd750108, and m pd75p0116 i can be used in only mk i mode for the m PD750104, m pd750106, m pd750108, and m pd75p0116 ii can be used in only mk ii mode for the m PD750104, m pd750106, m pd750108, and m pd75p0116 i/ii can be used in both mk i mode and mk ii mode for the m PD750104, m pd750106, m pd750108, and m pd75p0116. however, mk i mode is different from mk ii mode in the functions. read the explanation of [mk i mode] for mk i mode and the explanation of [mk ii mode] for mk ii mode, as required. remark " function " in this section is applicable to the m pd750106 and m pd750108 whose program counters consist of 13 bits each. this is also applicable to the m PD750104 whose program counter consists of 12 bits and the m pd75p0116 whose program counter consists of 14 bits, however. 11.4.1 transfer instructions mov a,#n4 function: a 269 chapter 11 instruction set mov reg1,#n4 function: reg1 270 m pd750108 user's manual then skips the immediately following instruction. when hlC (automatic decrement) is specified for the register pair, automatically decrements the contents of the l register by one after the data transfer, and continues the operation until the contents are set to fh. then skips the immediately following instruction. mov xa,@hl function: a 271 chapter 11 instruction set mov xa,mem function: a 272 m pd750108 user's manual mov reg1,a function: reg1 (register pair specified by the operand) when hl+ is specified for the register pair: skip if l = 0 when hlC is specified for the register pair: skip if l = fh exchanges the contents of the a register with the data at the data memory location addressed by the specified register pair (hl, hl+, hlC , de, dl). when hl+ (automatic increment) is specified for the register pair, automatically increments the contents of the l register by one after the data exchange, and continues the operation until the contents are set to 0. then skips the immediately following instruction. when hlC (automatic decrement) is specified for the register pair, automatically decrements the contents of the l register by one after the data exchange, and continues the operation until the contents are set to fh. then skips the immediately following instruction. example the data at addresses 20h-2fh are exchanged with the data at addresses 30h-3fh. sel mb0 mov d,#2 mov hl,#30h loop: xch a,@hl ; a (3x) xch a,@dl ; a (2x) xch a,@hl+ ; a (3x) br loop
273 chapter 11 instruction set xch xa,@hl function: a (hl), x (hl+1) exchanges the contents of the a register with the data at the data memory location addressed by the hl register pair, and exchanges the contents of the x register with the data at the next memory address. however, if the contents of the l register are odd- numbered, an address with the low-order bit ignored is specified. xch a,mem function: a (mem) mem = d 7-0 : 00h-feh exchanges the contents of the a register with the data at the data memory location addressed by the 8- bit immediate data mem. xch xa,mem function: a (mem), x (mem+1) mem = d 7-0 : 00h-feh exchanges the contents of the a register with the data at the data memory location addressed by the 8- bit immediate data mem, and exchanges the contents of the x register 1 with the data at the next memory address. an even address can be specified with mem. xch a,reg1 function: a reg1 exchanges the contents of the a register with register reg1 (x, h, l, d, e, b, c). xch xa,rp function: xa rp exchanges the contents of the xa register pair with the contents of register pair rp (xa, hl, de, bc, xa, hl, de, bc).
274 m pd750108 user's manual 11.4.2 table reference instructions movt xa,@pcde function: for the m pd750106 and m pd750108 xa PD750104 whose program counter consists of 12 bits and the m pd75p0116 whose program counter consists of 14 bits, however. caution the movt xa,@pcde instruction usually references table data in the page containing that instruction. however, when the instruction is located at address xxffh, table data in the next page is referenced instead of table data in the page containing that instruction. pc 12-8 d 3-0 e 3-0 8 7 4 3 0 12 table address table data h table data l x 30 a 30 4 3 70 program memory 70 program memory page 2 page 3 a 02ffh 0300h
275 chapter 11 instruction set for example, if movt xa,@pcde is located at a as shown above, the table data in page 3 specified by the contents of the de register pair is transferred to the xa register pair instead of that in page 2. example the 16-byte data at addresses xxf0h-xxffh in program memory is transferred to addresses 30h-4fh in data memory. sub: sel mb0 mov hl,#30h ; hl PD750104 whose program counter consists of 12 bits and the m pd75p0116 whose program counter consists of 14 bits, however.
276 m pd750108 user's manual movt xa,@bcxa function: for the m pd750106 and m pd750108 xa PD750104 whose program counter consists of 12 bits and the m pd75p0116 whose program counter consists of 14 bits, however. 11 12 8 7 4 3 0 b 0 cxa table data h table data l x 30 a 30 11 12 8 7 4 3 0 b 0 cde table data h table data l x 30 a 30
277 chapter 11 instruction set 11.4.3 bit transfer instructions mov1 cy,fmem.bit mov1 cy,pmem.@l mov1 cy,@h+mem.bit function: cy 278 m pd750108 user's manual adds xa,#n8 function: xa 279 chapter 11 instruction set addc xa,rp function: xa, cy 280 m pd750108 user's manual subs rp1,xa function: rp1 281 chapter 11 instruction set and a,@hl function: a 282 m pd750108 user's manual or rp1,xa function: rp1 283 chapter 11 instruction set 11.4.5 accumulator manipulation instructions rorc a function: cy <- a 0 , a n-1 <- a n , a 3 <- cy (n = 1-3) rotates the contents of the a register (4-bit accumulator) through the carry flag one bit position to the right. not a function: a 284 m pd750108 user's manual incs mem function: (mem) 285 chapter 11 instruction set ske xa,@hl function: skip if a = (hl) and x = (hl+1) skips the immediately following instruction if the contents of the a register match the data at the data memory location addressed by the hl register pair, and the contents of the x register match the data at the next address in data memory. however, if the contents of the l register are odd- numbered, an address with the lowest-order bit ignored is specified. ske a,reg function: skip if a = reg skips the immediately following instruction if the contents of the a register match the contents of register reg (x, a, h, l, d, e, b, c). ske xa,rp function: skip if xa = rp skips the immediately following instruction if the contents of the xa register pair match the contents of register pair rp (xa, hl, de, bc, xa, hl, de, bc). 11.4.8 carry flag manipulation instructions set1 cy function: cy 286 m pd750108 user's manual not1 cy function: cy 287 chapter 11 instruction set skt mem.bit function: skip if (mem.bit) = 1 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 1. skt fmem.bit skt pmem.@l skt @h+mem.bit function: skip if (bit specified in operand) = 1 skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@l, @h+mem.bit) is set to 1. skf mem.bit function: skip if (mem.bit) = 0 mem = d 7-0 : 00h-ffh, bit = b 1-0 : 0-3 skips the immediately following instruction if the bit specified by the 2-bit immediate data bit at the address specified by the 8-bit immediate data mem is 0. skf fmem.bit skf pmem.@l skf @h+mem.bit function: skip if (bit specified in operand) = 0 skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@l, @h+mem.bit) is 0. sktclr fmem.bit sktclr pmem.@l sktclr @h+mem.bit function: skip if (bit specified in operand) = 1 then clear skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing (fmem.bit, pmem.@l, @h+mem.bit) is 1, then clears the bit to 0.
288 m pd750108 user's manual and1 cy,fmem.bit and1 cy,pmem.@l and1 cy,@h+mem.bit function: cy 289 chapter 11 instruction set br addr1 function: for the m pd750108 pc 12-0 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). bra !addr1 function: for the m pd750108 pc 12-0 290 m pd750108 user's manual remark " function " in this section is applicable to the m pd750108 whose program counter consists of 13 bits (addr = 0000h to 1fffh). however, this is also applicable to the m PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). brcb !caddr function: for the m pd750108 pc 12-0 PD750104 consists of 11 bits, this instruction enables a branch to any location in the program memory space. in the m pd750106 and m pd750108, pc 12 cannot be changed, so no branch occurs beyond the block. similarly, in the m pd75p0116, pc 12 and pc 13 cannot be changed, so no branch occurs beyond the block. caution the brcb !caddr instruction usually causes a branch within the block containing the instruction. however, if the first byte is located at address 0ffeh or 0fffh, a branch to block 1 instead of block 0 occurs. if the brcb !caddr instruction is located at a or b in the figure above, a branch to block 1 instead of block 0 occurs. remark " function " in this section is applicable to the m pd750108 whose program counter consists of 13 bits (addr = 0000h to 1fffh). however, this is also applicable to the m PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). a b 70 program memory 0ffeh 0fffh 1000h block 0 block 1
291 chapter 11 instruction set br pcde function: for the m pd750108 pc 12-0 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). 70 program memory 02feh 02ffh 0300h page 2 page 3 a b
292 m pd750108 user's manual br bcde function: for the m pd750108 pc 12-0 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). b c 30 0 d 30 e 30 11 8 7 4 3 0 12 pc b c 30 0 x 30 a 30 11 8 7 4 3 0 12 pc
293 chapter 11 instruction set 11.4.11 subroutine stack control instructions calla !addr1 function: for the m pd750108 (spC2) PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). i/ii ii
294 m pd750108 user's manual callf !faddr function: for the m pd750108 [mk i mode] (spC1) PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). i/ii
295 chapter 11 instruction set ret function: for the m pd750108 [mk i mode] pc 11-8 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). rets function: for the m pd750108 [mk i mode] pc 11-8 296 m pd750108 user's manual remark " function " in this section is applicable to the m pd750108 whose program counter consists of 13 bits (addr = 0000h to 1fffh). however, this is also applicable to the m PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). reti function: for the m pd750108 [mk i mode] pc 11-8 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). push rp function: (spC1) 297 chapter 11 instruction set push bs function: (spC1) 298 m pd750108 user's manual di iexxx function: iexxx 299 chapter 11 instruction set caution before this instruction can be executed, mbe = 0 or (mbe = 1, mbs = 15) must be set. only 4 or 6 can be specified as n. 11.4.14 cpu control instructions halt function: pcc.2 300 m pd750108 user's manual geti taddr function: taddr = t 5-0 , 0 : 20h-7fh for the m pd750108 [mk i mode] ? when a table defined by the tbr instruction is referenced pc 12-0 PD750104 whose program counter consists of 12 bits (addr = 0000h to 0fffh), the m pd750106 whose program counter consists of 13 bits (addr = 0000h to 17ffh), and the m pd75p0116 whose program counter consists of 14 bits (addr = 0000h to 3fffh). the 2-byte data at the program memory addresses specified by (taddr) and (taddr+1) is referenced and executed as an instruction. addresses 0020h to 007fh are used as a reference table area. data must be written to this area beforehand. when a 1-byte instruction or 2-byte instruction is written, its mnemonic can be used directly. for a 3-byte call instruction or 3-byte branch instruction, an assembler pseudo instruction (tcall, tbr) is used. only an even address can be specified as taddr. i/ii
301 chapter 11 instruction set caution all 2-byte instructions (except the brcb instruction and callf instruction) set in the reference table must be 2-machine-cycle instructions. pairs of 1-byte instructions can be set as indicated in the table below. first byte instruction second byte instruction incs l mov a,@hl decs l mov @hl,a incs h xch a,@hl decs h incs hl incs e mov a,@de decs e incs d xch a,@de decs d incs de mov a,@dl incs l decs l xch a,@dl incs d decs d the pc is not incremented during execution of a geti instruction, so that after a reference instruction is executed, execution is resumed starting at the address immediately after the geti instruction. if the instruction immediately preceding a geti instruction has the skip function, the geti instruction is skipped as with other 1-byte instructions. if an instruction referenced with a geti instruction has the skip function, the instruction immediately following the geti instruction is skipped. if a geti instruction references an instruction having a string effect, the following processing is performed: ? if the instruction immediately preceding the geti instruction also has the string effect in the same group, the execution of the geti instruction cancels the string effect, and the referenced instruction is not skipped. ? if the instruction immediately following the geti instruction also has the string effect of the same group, the string effect of the referenced instruction remains valid, and the next instruction is skipped.
302 m pd750108 user's manual example mov hl, #00h mov xa, #ffh are replaced with geti instructions. call sub1 br sub2 org 20h hl00: mov hl, #00h xaff: mov xa, #ffh csub1: tcall sub1 bsub2: tbr sub2 get hl00 ; mov hl,#00h geti bsub2 ; br sub2 geti csub1 ; call sub1 geti xaff ; mov xa,#ffh
303 a appendix a functions of the m pd750008, m pd750108, and m pd75p0116 pin connection instruction execution time (1/2) item m pd750008 m pd750108 m pd75p0116 program memory masked rom one-time prom 0000h - 1fffh 0000h - 3fffh (8192 x 8 bits) (16384 x 8 bits) data memory 000h - 1ffh (512 x 4 bits) cpu 75xl cpu general-purpose register (4 bits x 8 or 8 bits x 4) x 4 banks main system clock oscillator crystal/ceramic rc oscillator (with external resistor and oscillator capacitor) time required for start after reset 2 17 /f x , 2 15 /f x fixed to 56/f cc (selected using a mask option) wait time applied when stop 2 20 /f x , 2 17 /f x , 2 15 /f x, 2 9 /f cc or no wait fixed to 2 9 /f cc mode is released by an interrupt 2 13 /f x (selected accord- (selected using a mask ing to btm setting) option) subsystem clock oscillator crystal oscillator when selecting the main 0.95, 1.91, 3.81, 15.3 4, 8, 16, 64 m s (when operating at 1 mhz) system clock m s (when operating at 4.19 mhz) 2, 4, 8, 32 m s (when operating at 2 mhz) 0.67, 1.33, 2.57 10.7 m s (when operating at 6.0 mhz) when selecting the 122 m s (when operating at 32.768 khz) subsystem clock 20 (cu) ic v pp 38 (gb) 24 (cu) p21/pto1 42 (gb) 6-9 (cu) p33 - p30 p33/md3 - p30/md0 23-26 (gb) 38-41 (cu) p43 - p40 p43/d3 - p40/d0 13-16 (gb) 34-37 (cu) p53 - p50 p53/d7 - p50/d4 8-11 (gb)
304 m pd750108 user's manual (2/2) i/o port item m pd750008 m pd750108 m pd75p0116 cmos input 8 (built-in pull-up resistors that can be connected by software: 7) cmos i/o 18 (built-in pull-up resistors that can be connected by software) n-ch open-drain i/o 8 (pull-up resistors that can be incorporated by 8 (no mask option) mask option) withstand voltage of withstand voltage of 13 v 13 v total 34 timer 4 channels 4 channels 8-bit timer counter: 1 8-bit timer counter (clock timer output function 8-bit timer/event provided): 1 counter: 1 8-bit timer/event counter: 1 basic interval timer/ basic interval timer/watchdog timer: 1 watchdog timer: 1 clock timer: 1 clock timer: 1 serial interface 3 modes supported three-wire serial i/o mode: first transferred bit switchable between lsb and msb two-wire serial i/o mode sbi mode clock output (pcl) f , 524, 262, 65.5 khz f , 125, 62.5, 15.6 khz (when the main system (when the main system clock operates at 1 mhz) clock operates at 4.19 mhz) f , 750, 375, 93.8 khz f , 250, 125, 31.3 khz (when the main system (when the main system clock operates at 2 mhz) clock operates at 6.0 mhz) buzzer output (buz) 2, 4, 32 khz (when the 2, 4, 32 khz (when the subsystem clock main system clock operates at 32.768 khz) operates at 4.19 mhz 0.488, 0.977, 7.813 khz (when the main or the subsystem clock system clock operates at 1 mhz) operates at 32.768 khz) 0.977, 1.953, 15.625 khz (when the main 2.93, 5.86, 46.9 khz system clock operates at 2 mhz) (when the main system clock operates at 6.0 mhz) vectored interrupt external: 3, internal: 4 test input external: 1, internal: 1 supply voltage v dd = 2.2 to 5.5 v v dd = 1.8 to 5.5 v operating ambient temperature t a = -40 to +85 c package 42-pin plastic shrink dip (600 mil) 44-pin plastic qfp (10 x 10 mm)
305 appendix b development tools the following development tools are provided for the development of a system which employs the m pd750108. in the 75xl series, use the common relocatable assembler together with a device file of each model. note these software products cannot use the task swap function, which is available in ms-dos ver. 5.00 or later. remark the operations of the assembler and device file are guaranteed only on the above host machines and oss. ra75x relocatable assembler host machine pc-9800 series ibm pc/at tm and compatibles distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc part number m s5a13ra75x m s5a10ra75x m s7b13ra75x m s7b10ra75x os ms-dos ver. 3.30 to ver. 6.2 note see " os for ibm pc ." device file host machine pc-9800 series ibm pc/at and compatibles distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hc 5.25-inch 2hc part number m s5a13df750008 m s5a10df750008 m s7b13df750008 m s7b10df750008 os ms-dos ver. 3.30 to ver. 6.2 note see " os for ibm pc ." b
306 m pd750108 user's manual prom programming tools note these software products cannot use the task swap function, which is available in ms-dos ver. 5.00 or later. remark operation of the pg-1500 controller is guaranteed only on the above host machines and oss. the pg-1500 prom programmer is used together with an accessory board and optional program adapter. it allows the user to program a single chip microcomputer containing prom from a standalone terminal or a host machine. the pg-1500 can be used to program typical 256k-bit to 4m-bit proms. the pa-75p008cu is a prom programmer adapter provided for the m pd75p0116cu/gb. it is used in conjunction with the pg-1500. this program enables the host machine to control the pg-1500 through the serial and parallel interfaces. hardware software pg-1500 pa-75p008cu pg-1500 controller distribution media 3.5-inch 2hd 5.25-inch 2hd 3.5-inch 2hd 5.25-inch 2hc os ms-dos ver. 3.30 to ver. 6.2 note see " os for ibm pc ." part number m s5a13pg1500 m s5a10pg1500 m s7b13pg1500 m s7b10pg1500 host machine pc-9800 series ibm pc/at and compatibles
307 appendix b development tools the ie-75000-r is an in-circuit emulator used to debug hardware and software when developing an application system using the 75x series and 75xl series. use this emulator together with optional emulation board ie-75300-r-em and emulation probe to develop application systems of the m pd750108 subseries. for efficient debugging, connect the emulator to the host machine and a prom programmer. the ie-75000-r contains emulation board ie-75000-r-em. the board is connected to the ie-75000-r. the ie-75001-r is an in-circuit emulator used to debug hardware and software when developing an application system using the 75x series and 75xl series. use this emulator together with optional emulation board ie-75300-r-em and emulation probe. for efficient debugging, connect the emulator to the host machine and a prom programmer. the ie-75300-r-em is an emulation board used to evaluate an application system using the m pd750108 subseries. use this board together with the ie-75000-r or ie-75001-r. the ep-75008gb-r is an emulation probe for the m pd750108gb. connect this emulation probe to the ie-75000-r or ie-75001-r, and the ie- 75300-r-em. a 44-pin conversion socket, the ev-9200g-44, supplied with this probe facili- tates the connection of the probe to the target system. the ep-75008cu-r is an emulation probe for the m pd750108cu. connect this emulation probe to the ie-75000-r or ie-75001-r, and the ie- 75300-r-em. this program enables the host machine to control the ie-75000-r or ie-75001- r through the rs-232-c and centronics interface. hardware debugging tools the in-circuit emulators (ie-75000-r and ie-75001-r) are provided to debug programs used for the m pd750108. the following system is shown below. notes 1. maintenance service only 2. these software products cannot use the task swap function, which is available in ms dos ver. 5.00 or later. remarks 1. operation of the ie control program is guaranteed only on the above host machines and oss. 2. the m PD750104, m pd750106, m pd750108, and m pd75p0116 are collectively referred to as the m pd750108 subseries. see os for ibm pc . 3.5-inch 2hd 5.25-inch 2hd m s5a13ie75x m s5a10ie75x distribution media part number host machine ibm pc/at and compatibles 3.5-inch 2hc 5.25-inch 2hc m s7b13ie75x m s7b10ie75x os ms-dos ver. 3.30 to ver. 6.2 note 2 pc-9800 series ie-75000-r note 1 ie-75001-r ie-75300-r-em ep-75008gb-r ev-9200g-44 ep-75008cu-r ie control program software
308 m pd750108 user's manual os for ibm pc the following ibm pc oss are supported. os version pc dos ver. 5.02 to ver. 6.3 j6.1/v note to j6.3/v note ms-dos ver. 5.0 to ver. 6.22 5.0/v note to 6.2/v note ibm dos tm j5.02/v note note only english version is supported. caution these software products cannot use the task swap function, which is available in ms-dos ver. 5.00 or later.
309 appendix b development tools target system note 2 emulation probe ep-75008cu-r ep-75008gb-r in-circuit emulator ie-75000-r or ie-75001-r emulation board ie-75300-r-em note 1 product containing prom pd75p0116cu prom programmer pg-1500 + programmer adapter pa-75p008cu rs-232-c centronics interface ie control program pg-1500 controller host machine pc-9800 series ibm pc/at (symbolic debugging is possible.) pd75p0116gb the in-circuit emulators do not contain the ie-75300-r-em (to be ordered). ev-9200g-44 development tool configuration device file relocatable assembler + 2. notes 1.
310 m pd750108 user's manual drawings of the conversion socket (ev-9200g-44) and recommended pattern on boards figure b-1. drawings of the ev-9200g-44 (reference) a f d 1 e ev-9200g-44 b c m n o l k r q i h p j g ev-9200g-44-g0 item millimeters inches a b c d e f g h i j k l m o n p q r 15.0 10.3 10.3 15.0 4-c 3.0 0.8 5.0 12.0 14.7 5.0 12.0 14.7 8.0 7.8 2.0 1.35 0.35 0.1 1.5 0.591 0.406 0.406 0.591 4-c 0.118 0.031 0.197 0.472 0.579 0.197 0.472 0.579 0.315 0.307 0.079 0.053 0.014 0.059 +0.004 e0.005 f f no.1 pin index based on ev-9200g-44 (1) package drawing (in mm)
311 appendix b development tools figure b-2. recommended pattern on boards for the ev-9200g-44 (reference) caution dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). 0.031 0.394=0.315 0.031 0.394=0.315 a f d e b g h i j c l k ev-9200g-44-p1e item millimeters inches a b c d e f g h i j k l 15.7 11.0 11.0 15.7 5.00 0.08 5.00 0.08 0.5 0.02 1.57 0.03 2.2 0.1 1.57 0.03 0.618 0.433 0.433 0.618 0.197 0.197 0.02 0.062 0.087 0.062 0.8 0.02 10=8.0 0.05 0.8 0.02 10=8.0 0.05 f f f +0.002 e0.001 +0.002 e0.002 +0.002 e0.001 +0.002 e0.002 +0.003 e0.004 +0.003 e0.004 +0.001 e0.002 f f f +0.001 e0.002 +0.004 e0.005 +0.001 e0.002 dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution based on ev-9200g-44 (2) pad drawing (in mm)
312 m pd750108 user's manual [memo]
313 appendix c masked rom ordering procedure after program development is completed, the masked rom is ordered by the following procedure: <1> advance notice of an order for masked rom give advance notice of masked rom ordering to a special agent or necs sales department, otherwise the ordered products may be delivered with delay. <2> preparation of media for ordering masked rom orders can be placed on the following media types. ? uv-eprom note ? 3.5-inch ibm format floppy disk (outside japan only) ? 5.25-inch ibm format floppy disk (outside japan only) note when the uv-eprom option is selected, prepare three uv-eproms each having the same contents. record the mask option data on the mask option information sheet. <3> preparation of the required documents prepare the following documents when ordering a masked rom: ? masked rom order sheet ? masked rom order check sheet ? mask option information sheet <4> ordering send a set of the media created in <2> and the documents created in <3> to a special agent or necs sales department by the date indicated in the advance notice. c *
314 m pd750108 user's manual [memo]
315 appendix d instruction index d.1 instruction index (by function) [transfer instructions] mov a,#n4 ... 249, 268 mov reg1,#n4 ... 249, 269 mov xa,#n8 ... 249, 269 mov hl,#n8 ... 249, 269 mov rp2,#n8 ... 249, 269 mov a,@hl ... 249, 269 mov a,@hl+ ... 249, 269 mov a,@hlC ... 249, 269 mov a,@rpa1 ... 249, 269 mov xa,@hl ... 249, 270 mov @hl,a ... 249, 270 mov @hl,xa ...249, 270 mov a,mem ... 249, 270 mov xa,mem ... 249, 271 mov mem,a ... 249, 271 mov mem,xa ... 249, 271 mov a,reg ... 249, 271 mov xa,rp ... 249, 271 mov reg1,a ... 249, 272 mov rp1,xa ... 249, 272 xch a,@hl ... 249, 272 xch a,@hl+ ... 249, 272 xch a,@hlC ... 249, 272 xch a,@rpa1 ... 249, 272 xch xa,@hl ... 249, 273 xch a,mem ... 249, 273 xch xa,mem ... 249, 273 xch a,reg1 ... 249, 273 xch xa,rp ...249, 273 [table reference instructions] movt xa,@pcde ... 250, 274 movt xa,@pcxa ... 250, 275 movt xa,@bcde ... 250, 276 movt xa,@bcxa ... 250, 276 [bit transfer instructions] mov1 cy,fmem.bit ... 250, 277 mov1 cy,pmem.@l ... 250, 277 mov1 cy,@h+mem.bit ... 250, 277 mov1 fmem.bit,cy ... 250, 277 mov1 pmem.@l,cy ... 250, 277 mov1 @h+mem.bit,cy ... 250, 277 [arithmetic/logical instructions] adds a,#n4 ... 250, 277 adds xa,#n8 ... 250, 278 adds a,@hl ... 250, 278 adds xa,rp ... 250, 278 adds rp1,xa ... 250, 278 addc a,@hl ... 250, 278 addc xa,rp ... 250, 279 addc rp1,xa ... 250, 279 subs a,@hl ... 250, 279 subs xa,rp ... 250, 279 subs rp1,xa ... 250, 280 subc a,@hl ... 250, 280 subc xa,rp ... 250, 280 subc rp1,xa ... 250, 280 and a,#n4 ... 251, 280 and a,@hl ... 251, 281 and xa,rp ...251, 281 and rp1,xa... 251, 281 or a,#n4 ... 251, 281 d
316 m pd750108 user's manual or a,@hl ... 251, 281 or xa,rp ... 251, 281 or rp1,xa ... 251, 282 xor a,#n4 ... 251, 282 xor a,@hl ... 251, 282 xor xa,rp ... 251, 282 xor rp1,xa ... 251, 282 [accumulator manipulation instructions] rorc a ... 251, 283 not a ... 251, 283 [increment/decrement instructions] incs reg ... 251, 283 incs rp1 ... 251, 283 incs @hl ... 251, 283 incs mem ... 251, 284 decs reg ... 251, 284 decs rp ... 251, 284 [compare instructions] ske reg,#n4 ... 251, 284 ske @hl,#n4 ... 251, 284 ske a,@hl ... 251, 284 ske xa,@hl ... 251, 285 ske a,reg ... 251, 285 ske xa,rp ... 251, 285 [carry flag manipulation instructions] set1 cy ... 251, 285 clr1 cy ... 251, 285 skt cy ... 251, 285 not1 cy ... 251, 286 [memory bit manipulation instructions] set1 mem.bit ... 252, 286 set1 fmem.bit ... 252, 286 set1 pmem.@l ... 252, 286 set1 @h+mem.bit ... 252, 286 clr1 mem.bit ... 252, 286 clr1 fmem.bit ... 252, 286 clr1 pmem.@l ... 252, 286 clr1 @h+mem.bit ... 252, 286 skt mem.bit ... 252, 287 skt fmem.bit ... 252, 287 skt pmem.@l ... 252, 287 skt @h+mem.bit ... 252, 287 skf mem.bit ... 252, 287 skf fmem.bit ... 252, 287 skf pmem.@l ... 252, 287 skf @h+mem.bit ... 252, 287 sktclr fmem.bit ... 252, 287 sktclr pmem.@l ... 252, 287 sktclr @h+mem.bit ... 252, 287 and1 cy,fmem.bit ... 252, 288 and1 cy,pmem.@l ... 252, 288 and1 cy,@h+mem.bit ... 252, 288 or1 cy,fmem.bit ... 252, 288 or1 cy,pmem.@l ... 252, 288 or1 cy,@h+mem.bit ... 252, 288 xor1 cy,fmem.bit ... 252, 288 xor1 cy,pmem,@l ... 252, 288 xor1 cy,@h+mem.bit ... 252, 288 [branch instructions] br addr ... 253, 288 br addr1 ... 253, 289 br !addr ... 254, 289 br $addr ... 254, 289 br $addr1 ... 254, 289 br pcde ... 254, 291 br pcxa ... 254, 291 br bcde ... 254, 292 br bcxa ... 255, 292
317 bra !addr1 ... 255, 289 brcb !caddr ... 255, 290 tbr addr ... 260, 292 [subroutine stack control instructions] calla !addr1 ... 255, 293 call !addr ... 256, 293 callf !faddr ... 256, 294 tcall !addr ... 260, 294 ret ... 257, 295 rets ... 258, 295 reti ... 258, 296 push rp ... 259, 296 push bs ... 259, 297 pop rp ... 259, 297 pop bs ... 259, 297 [interrupt control instructions] ei ... 259, 297 ei iexxx ... 259, 297 di ... 259, 297 di iexxx ... 259, 298 [i/o instructions] in a,portn ... 259, 298 in xa,portn ... 259, 298 out portn,a ... 259, 298 out portn,xa ... 259, 298 [cpu control instructions] halt ... 259, 299 stop ... 259, 299 nop ... 259, 299 [special instructions] sel rbn ... 260, 299 sel mbn ... 260, 299 geti taddr ... 260, 300 appendix d instruction index
318 m pd750108 user's manual d.2 instruction index (alphabetical order) [a] addc a,@hl ... 250, 278 addc rp1,xa .. 250, 279 addc xa,rp ... 250, 279 adds a,#n4 ... 250, 277 adds a,@hl ... 250, 278 adds rp1,xa ... 250, 278 adds xa,rp ... 250, 278 adds xa,#n8 ... 250, 278 and a,#n4 ... 251, 280 and a,@hl ... 251, 281 and rp1,xa ... 251, 281 and xa,rp ... 251, 281 and1 cy,fmem.bit ... 252, 288 and1 cy,pmem.@l ... 252, 288 and1 cy,@h+mem.bit ... 252, 288 [b] br addr ... 253, 288 br addr1 ... 253, 289 br bcde ... 254, 292 br bcxa ... 255, 292 br pcde ... 254, 291 br pcxa ... 254, 291 br !addr ... 254, 289 br $addr ... 254, 289 br $addr1 ... 254, 289 bra !addr1 ... 255, 289 brcb !caddr ... 255, 290 [c] call !addr ... 256, 293 calla !addr1 ... 255, 293 callf !faddr ... 256, 294 clr1 cy ... 251, 285 clr1 fmem.bit ... 252, 286 clr1 mem.bit ... 252, 286 clr1 pmem.@l ... 252, 286 clr1 @h+mem.bit ... 252, 286 [d] decs reg ... 251, 284 decs rp ... 251, 284 di ... 259, 297 di iexxx ... 259, 298 [e] ei ... 259, 297 ei iexxx ... 259, 297 [g] geti taddr ... 260, 300 [h] halt ... 259, 299 [i] in a,portn ... 259, 298 in xa,portn ... 259, 298 incs mem ... 251, 284 incs reg ... 251, 283 incs rp1 ... 251, 283 incs @hl ... 251, 283 [m] mov a,mem ... 249, 270 mov a,reg ... 249, 271 mov a,#n4 ... 249, 268 mov a,@hl ... 249, 269 mov a,@hl+ ... 249, 269 mov a,@hlC ... 249, 269
319 mov a,@rpa1 ... 249, 269 mov hl,#n8 ... 249, 269 mov mem,a ... 249, 271 mov mem,xa ... 249, 271 mov reg1,a ... 249, 272 mov reg1,#n4 ... 249, 269 mov rp1,xa ... 249, 272 mov rp2,#n8 ... 249, 269 mov xa,mem ... 249, 271 mov xa,rp ... 249, 271 mov xa,#n8 ... 249, 269 mov xa,@hl ... 249, 270 mov @hl,a ... 249, 270 mov @hl,xa ... 249, 270 movt xa,@bcde ... 250, 276 movt xa,@bcxa ... 250, 276 movt xa,@pcde ... 250, 274 movt xa,@pcxa ... 250, 275 mov1 cy,fmem.bit ... 250, 277 mov1 cy,pmem.@l ... 250, 277 mov1 cy,@h+mem.bit ... 250, 277 mov1 fmem.bit,cy ... 250, 277 mov1 pmem.@l,cy ... 250, 277 mov1 @h+mem.bit,cy ... 250, 277 [n] nop ... 259, 299 not a ... 251, 283 not1 cy ... 251, 286 [o] or a,#n4 ... 251, 281 or a,@hl ... 251, 281 or rp1,xa ... 251, 282 or xa,rp ... 251, 281 or1 cy,fmem.bit ... 252, 288 or1 cy,pmem.@l ... 252, 288 or1 cy,@h+mem.bit ... 252, 288 out portn,a ... 259, 298 out portn,xa ... 259, 298 [p] pop bs ... 259, 297 pop rp ... 259, 297 push bs ... 259, 297 push rp ... 259, 296 [r] ret ... 257, 295 reti ... 258, 296 rets ... 258, 295 rorc a ... 251, 283 [s] sel mbn ... 260, 299 sel rbn ... 260, 299 set1 cy ... 251, 285 set1 fmem.bit ... 252, 286 set1 mem.bit ... 252, 286 set1 pmem.@l ... 252, 286 set1 @h+mem.bit ... 252, 286 ske a,reg ... 251, 285 ske a,@hl ... 251, 284 ske reg,#n4 ... 251, 284 ske xa,rp ... 251, 285 ske xa,@hl ... 251, 285 ske @hl,#n4 ... 251, 284 skf fmem.bit ... 252, 287 skf mem.bit ... 252, 287 skf pmem.@l ... 252, 287 skf @h+mem.bit ... 252, 287 skt cy ... 251, 285 skt fmem.bit ... 252, 287 skt mem.bit ... 252, 287 appendix d instruction index
320 m pd750108 user's manual skt pmem.@l ... 252, 287 skt @h+mem.bit ... 252, 287 sktclr fmem.bit ... 252, 287 sktclr pmem.@l ... 252, 287 sktclr @h+mem.bit ... 252, 287 stop ... 259, 299 subc a,@hl ... 250, 280 subc rp1,xa ... 250, 280 subc xa,rp ... 250, 280 subs a,@hl ... 250, 279 subs rp1,xa ... 250, 280 subs xa,rp ... 250, 279 [t] tbr addr ... 260, 292 tcall !addr ... 260, 294 [x] xch a,mem ... 249, 273 xch a,reg1 ... 249, 273 xch a,@hl ... 249, 272 xch a,@hl+ ... 249, 272 xch a,@hlC ... 249, 272 xch a,@rpa1 ... 249, 272 xch xa,mem ... 249, 273 xch xa,rp ... 249, 273 xch xa,@hl ... 249, 273 xor a,#n4 ... 251, 282 xor a,@hl ... 251, 282 xor rp1,xa ... 251, 282 xor xa,rp ... 251, 282 xor1 cy,fmem.bit ... 252, 288 xor1 cy,pmem,@l ... 252, 288 xor1 cy,@h+mem.bit ... 252, 288
321 appendix e hardware index e.1 hardware index (alphabetical order with respect to the hardware name) int1 edge detection mode register (im1) ... 197 int1 interrupt enable flag (ie1) ... 191 int1 interrupt request flag (irq1) ... 191 int2 edge detection mode register (im2) ... 217 int2 interrupt enable flag (ie2) ... 214 int2 interrupt request flag (irq2) ... 214 int4 interrupt enable flag (ie4) ... 191 int4 interrupt request flag (irq4) ... 191 [k] key interrupt input (kr0-kr7) ... 215 [m] memory bank enable flag (mbe) ... 23, 66 memory bank select register (mbs) ... 23, 67 [p] port 0 to port 8 (port0-port8) ... 70 port mode register group a (pmga) ... 77 port mode register group b (pmgb) ... 77 port mode register group c (pmgc) ... 77 processor clock control register (pcc) ... 88 program counter (pc) ... 49 program status word (psw) ... 64 pull-up resistor specification register group a (poga) ... 84 pull-up resistor specification register group b (pogb) ... 84 e [a] acknowledge detection flag (ackd) ... 135 acknowledge enable bit (acke) ... 135 acknowledge trigger bit (ackt) ... 135 [b] bank select register (bs) ... 67 basic interval timer (bt) ... 103 basic interval timer mode register (btm) ... 103 bit sequential buffer (bsb0-bsb3) ... 184 bt interrupt enable flag (iebt) ... 191 bt interrupt request flag (irqbt) ... 191 bus release detection flag (reld) ... 136 bus release trigger bit (relt) ... 136 busy enable bit (bsye) ... 135 [c] carry flag (cy) ... 64 clock mode register (wm) ... 109 clock output mode register (clom) ... 101 command detection flag (cmdd) ... 135 command trigger bit (cmdt) ... 136 [i] interrupt enable flag for clock timer (iew) ... 214 interrupt master enable flag (ime) ... 193 interrupt priority specification register (ips) ... 192 interrupt request flag for clock timer (irqw) ... 214 interrupt status flag (ist0, ist1) ... 65, 198 int0 edge detection mode register (im0) ... 197 int0 interrupt enable flag (ie0) ... 191 int0 interrupt request flag (irq0) ... 191
322 m pd750108 user's manual timer/event counter 0 mode register (tm0) ... 114 timer/event counter 0 modulo register (tmod0) ... 112 timer/event counter 0 output enable flag (toe0) ... 117 [w] wake-up function specification bit (wup) ... 131 watchdog timer enable flag (wdtm) ... 105 [r] register bank enable flag (rbe) ... 36, 66 register bank select register (rbs) ... 36, 67 [s] serial bus interface control register (sbic) ... 134 serial interface interrupt enable flag (iecsi) ... 191 serial interface interrupt request flag (irqcsi) ... 191 serial interface operation enable/disable specification bit (csie) ... 131 serial operation mode register (csim) ... 130 shift register (sio) ... 137 signal from address comparator (coi) ... 131 skip flag (sk0-sk2) ... 65 slave address register (sva) ... 137 stack bank select register (sbs) ... 48, 60 stack pointer (sp) ... 60 sub-oscillator control register (sos) ... 97 system clock control register (scc) ... 90 [t] timer counter 1 interrupt enable flag (iet1) ... 191 timer counter 1 interrupt request flag (irqt1) ... 191 timer counter 1 count register (t1) ... 113 timer/event counter 1 mode register (tm1) ... 114 timer counter 1 modulo register (tmod1) ... 113 timer/event counter 1 output enable flag (toe1) ... 117 timer/event counter 0 count register (t0) ... 112 timer/event counter 0 interrupt enable flag (iet0) ... 191 timer/event counter 0 interrupt request flag (irqt0) ... 191
323 e.2 hardware index (alphabetical order with respect to the hardware symbol) appendix e hardware index [a] ackd ... 135 acke ... 135 ackt ... 135 [b] bs ... 67 bsb0-bsb3 ... 184 bsye ... 135 bt ... 103 btm ... 103 [c] clom ... 101 cmdd ... 135 cmdt ... 136 coi ... 131 csie ... 131 csim .. 130 cy ... 64 [i] ie0 ... 191 ie1 ... 191 ie2 ... 214 ie4 ... 191 iebt ... 191 iecsi ... 191 iet0 ... 191 iet1 ... 191 iew ... 214 im0, im1 ... 197 im2 ... 217 ime ... 193 ips ... 192 irq0 ... 191 irq1 ... 191 irq2 ... 214 irq4 ... 191 irqbt ... 191 irqcsi ... 191 irqt0 ... 191 irqt1 ... 191 irqw ... 214 ist0 ... 65, 198 ist1 ... 65, 198 [k] kr0-kr7 ... 215 [m] mbe ... 23, 66 mbs ... 23, 67 [p] pc ... 49 pcc ... 88 pmga ... 77 pmgb ... 77 pmgc ... 77 poga ... 84 pogb ... 84 port0-port8 ... 70 psw ... 64 [r] rbe ... 36, 66 rbs ... 36, 67 reld ... 136 relt ... 136
324 m pd750108 user's manual [s] sbic ... 134 sbs ... 48, 60 scc ... 90 sio ... 137 sk0, sk1, sk2 ... 65 sos ... 97 sp ... 60 sva ... 137 [t] t0 ... 112 t1 ... 113 toe0 ... 117 toe1 ... 117 tm0 ... 114 tm1 ... 114 tmod0 ... 112 tmod1 ... 113 [w] wdtm ... 105 wm ... 109 wup ... 131
325 f appendix f revision history the revision history is shown below. the chapters described in the revised-chapter column indicate those for the corresponding edition. edition major changes revised chapter second the m PD750104, m pd750106, m pd750108, and m pd75p0116 have throughout already been developed. the data bus pins (d0-d7) have been added. connection of unused pins has been changed. chapter 2 writing to the program memory has been changed. chapter 9 reading the program memory has been changed. the target to be compared has been changed from the m pd75008 appendix a to m pd750008. *
326 m pd750108 user's manual [memo]
327 although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-889-1689 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec corporation semiconductor solution engineering division technical information support dept. fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 96.8 name company from: tel. fax facsimile message
328 m pd750108 user's manual